Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer, while not sacrificing performance (i.e. program, erase and read efficiencies and reliabilities). It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. It is also known to form trenches into the substrate, and locate one or more memory cell elements in the trench to increase the number of memory cells that fit into a given unit surface area (see for example U.S. Pat. Nos. 5,780,341 and 6,891,220). However, such memory cells use the control gate to both control the channel region (in a low voltage operation) and to erase the floating gate (in a high voltage operation). This means the control gate is both a low voltage and high voltage element, making it difficult to surround it with sufficient insulation for high voltage operation while not being too electrically isolated for low voltage operation. Moreover, the proximity of the control gate to the floating gate needed for an erase operation can result in unwanted levels of capacitive coupling between the control gate and the floating gate.
U.S. Pat. No. 8,148,768 discloses a memory device and method of making same, in which a trench is formed into a substrate 10 of semiconductor material. The source region 46 is formed under the trench, and the channel region 72 between the source and drain regions includes a first portion 72a that extends substantially along a sidewall of the trench and a second portion 72b that extends substantially along the surface of the substrate. The floating gate 42 is disposed in the trench, and is insulated from the channel region first portion 72a for controlling its conductivity. The control gate 62 is disposed over and insulated from the channel region second portion 72b, for controlling its conductivity. The erase gate 58 is disposed at least partially over and insulated from the floating gate 42. The erase gate 58 includes a notch 80, and the floating gate includes an edge 42a that directly faces and is insulated from the notch 80. Poly block 50 is formed at the bottom of the trench, and in electrical contact with source region 46, to provide the same voltage of source region 46 to poly block 50. Poly blocks 50 each extend along and are insulated from floating gates 42, for enhanced voltage coupling therebetween which is critical for programming and erasing the memory cell.
As the dimensions of the above described cell become smaller and smaller, several issues arise. First, there is a low source junction breakdown, which limits the program-disturb window. Second, the source voltage must be high enough to avoid programming disturb, which means the programming window is limited.
Thus it is an object of the present invention to create a memory cell configuration and method of manufacture that addresses these issues.